The Sound of Music

 One of the "funnest" projects I did was to build a Direct digital synthesizer (DDS). This part takes in a digital control word and provides a sine wave output. The frequency of the sine wave is proportional to the digital control word. Apparently one of the customers was a  toy manufacturer manufacturing musical toys spewing out classic songs. It is interesting but us engineers tend to skimp over applications of our ICs - you'd be surprised how many different ideas people can come up with (especially if your product is marked for the consumer space)

This part had digital logic, memory (ROM to store the sine codes) as well as DACs, buffers and amplifiers. In essence it was an SOC even before that term had been coined :-) At that time there was no AMS flow. In fact the company did not even have a verilog license (given the analog roots).  Thankfully we did have waveform viewers on screen and not reams of paper to look at (that was my undergrad school!).

Most of the time was spent on the current steering DAC and opamps (used in the low pass filter and the drivers). The customer wanted at least 50db of output fidelity so that translated back into quantization noise and DAC resolution/accuracy. The rest of the time was spent making sure that spice converged :-) No, it wasn't that bad but we did have clunky tools - making sure we actually knew how spice worked. I could design and simulate the individual blocks well but spice used to choke when doing a full chip simulation (remember everything including the memory block was in schematic form). Then you needed multiple cycles to actually do an FFT and make sure your fidelity is not broken. Ugh!

It took me about 5 months of design and layout supervision to get it to fab. I was proud of being the sole designer on it. In hindsight I can now appreciate how much EDA tools have helped increase productivity and made possible much more complicated ICs. AMS, verilogA, database sharing - some of my favourites. More of these in a late blog.

All the functionality and specification was met. However, one of the clock outputs (used only for debug/test) was showing a voltage swing between 5 and .5V (instead of 5 and 0). After beating down on the board designer and finding no leakage paths, I went back to my schematics and layout. To make a long story short, turns out one of the nmos transistors was not connected to ground but to the substrate which ultimately got connected to ground (but via a high Impedence path).

I miss the simplicity of being sole designer on an IC but I don't miss the EDA tools of that time.