PLL - Just another control system

A  PLL is just another control system which works in the phase domain, ie it trys to make the phase of the output approach that of the input. phase locked loop. Viewing thus you can answer many fundamental questions on the usage and properties of a PLL. For instance, what happens to step response? Why or why not is a PLL stable? Why do you need a zero in a gardner type PLL etc etc

So how does one go about designing a PLL - whether in IC form or discrete.

a) Get your system level specifications. What is your reference frequency? What about your Output frequency. Application - RF, serdes etc.

b) From there you can find your system parameters - Bandwidth, constraints (power, area etc)

c) This gives you an idea what architecture you need for the sub-blocks. For example, VCO - ring oscillator, LC and what sub-types (quadrature, varactor based etc)

d) Follow-up with designing these components, do block level simulations and finally system level simulations for specifications such as Power, Jitter. And lots of iterations.

Simple, right :-)

Some good books for the beginner to advanced

Beginner book

1) Phase locked Loops - design, simulation and applications

Advanced Book

2) Phase Lock Techniques, 3rd ed

There is a host of literature on this topic and my list is by no means comprehensive.

I have been building PLLs since 1997 in various technologies and applications.

I remember one of the first PLLs that I helped out on was for a 622Mb/s Sonet transceiver. This was a conventional Ring oscillator based PLL. The loop filter was fully differential and it fed a v2i (voltage to current converter) that fed a current starved Ring oscillator. The PFD was your typical 2 Flop one with a delayed reset.

One of the most fundamental changes in PLLs has been the growth of LCPLLs. I remember that when inductors were first used for PLL VCOs in commercial products, they were viewed as  risky. Nowdays you see them even in microprocessors on digital substrates with massive amount of switching noise.  By my estimate this took ~7years.

I have had the fortune to design inductor based PLLs in multiple generations of VDSM (very deep sub-micron) CMOS. My latest project was for a PCIe  LCPLL. The usual challenges of low jitter, power, area etc. were compounded by PCIe requirement of tight control on loop Bandwidth. Now, the trouble arises because of a few reasons

a) Varactor modeling and variation lead to large variation in Kvco

b) Charge pump are not really current source but charge sources. Due to finite rise, fall times etc. the "effective" current from a charge pump is not the same as current source/sink

c) Variation in loop filter Resistance

So some innovative solutions need to be used to meet the specifications. Some  ideas include

- methods to measure PLL Bandwidth and peaking on-die and auto-calibrate out errors

- Linearizing Kvco through ac-coupling caps

- Increasing charge pump switching speeds by moving away from cascode switching

- Using schemes which don't have a loop resistance. Examples: Self-biased or Sample-reset filters

Also do remember to use the correct Charge pump (HiZ) and VCO (LC VCO) to get your jitter low enough to meet your jitter requirements.

Drop me a note in case you want more ideas on the effectiveness of certain techniques to meet your architectural specifications.

There are quite a few articles out there on PLLs. However, finding an article on debuggability/ practical issues with PLLs is not readily available. So I am listing a few

a) Make Feedback divider faster than VCO. At startup your VCO might have a railed control voltage and may run much faster than you simulated for

b) Shield your VCO input control voltage. This is your most sensitive node. If you want to bring it for observability put a low leakage buffer on this pin

c) Avoid chicken-and-egg problems. When integrating the PLL with your ASIC your ASIC may depend upon a clean PLL clock to propogate certain states to the PLL boundary whereas the PLL may need certain states from the ASIC to lock. A way out is to use a local non-PLL clock (eg ring oscillator) just for propogating the states till the PLLs lock

d) Modeling PLL in RTL should take into account any states which cause PLL to shift frequencies or loose lock. It is not feasible to model PLL locking in a simulation involving a full-SoC. However, a basic model should involve all signals which can cause PLL to drift.

e) Model PLL in matlab etc. to ensure your PLL is always going to be stable and ideally have a damping factor > .8 in the worst case. Remember to take aging into account when doing this.

I have just scratched the surface for this very important mixed-signal component. There are host of other nuanes - for example, testing PLLs with 300fs jitter (really!), modeling/comprehending various forms of jitter etc. etc. My next topic will focus on the future of PLLs and give a flavour of how PLL techniques can be used to analyze other components (such as clock data recovery)

Remember debugging a PLL is very difficult since its a feedback loop. Be thorough and diligent in all your circuit and system level checks. Good luck!