Equalizer - Not your average sports term

Equalizer - A goal scored in the final seconds of a pulsating soccer match putting two great teams on an even kneel

Equalizer - A critical circuit allowing a far away viewer to see/hear the match with adaquate fidelity in real time

My first brush with an equalizer was in my graduate years where I designed and fabricated my first ever IC. Carnegie Mellon had a disk drive center which was looking at techniques to increase the capacity of drives. As you start increasing the denisty of recording, the adjacent bits start to "nudge" each other. This term ISI (inter symbol interference) causes you to read a 0 as 1 or vice-versa. An equalizer is a block to remove the ISI and regain your bits.

I designed the backward equalizer part of the DFE. We wanted to build something that was at least 50MHz to go along with another PhD students' Front End equalizer. I used a simple current steering mechanism as the fastest method. By doing it in current domain we could a simple subtraction of the post-cursor bits. One of the key challenges was building test circuitry since we could only send in PRBS data from external instruments but we needed to create distorted currents on chip. In any case I was able to run through the whole IC fabrication method (Thanks Mosis) and actually got to check the performance in the lab. We published the results and could hit speeds approaching 66MHz. Seems so ancient by today's standards. In any case, Check it out in IEEE JSSC under my name.

Another opportunity I got was building a Receive Equalizer for 100baseTx transceiver. 100BaseT had just arrived and my employer had built a BiCMOS Transceiver which was wildely successful. Unfortunately CMOS versions were coming around and we needed to build a lower power BiCMOS one in a quad form-factor (put four of them together in one package). The way to lower the power was to decrease the Supply voltage. This is tricky because of  the .7V in Vbe. You just can't get around it. And you end up building all these level shifters, emitter followers, diff pairs for high speed circuits and end up needing larger Vss/Vee. A way around this to do use more of current folding schemes.

So the idea was to use folded cascode structures and lower the supply voltage from 5V to 3V. The equalizer consisted of gm-C filters and had a split high peaking and low peaking path. By relative weighting between these two paths, you could achieve an adaptive equalizer for any length of Cat5 cable between 0 to 120m.

One of the nasty bugs we had was that in some parts the output of the equalizer was always stuck at 1. Of course simulations didn't predict this. After countless sleepless days, it was discovered that offset of one of the stages was causing the equalizer output to saturate. Finding this was such a pain. Fib and then put in an external voltage source to try to tune out the offset. Using pico-probes and then making sure things did not move once you were able to hit those probe pads - ah the joys. In any case, a stepping fixed it. While an analog approach, this product worked very well and was again a commercial success. Even today in the age of 32nm and below CMOS, preceeding a Digital DSP equalizer/ADC combo with a small, simple analog equalizer can provide savings in terms of power and complexity. Thats my claim and I am sticking with it!

I also designed a 10G transmit equalizers. The cool thing about Tx equalizers is that they are much easier to design and understand. Just put a 1UI delay and a scaled replica and you are done (for 1 tap filter). However, as is usual, there is more than meets the eye. One of the trends is to use a parallel approach with a Look-up table instead of a serial multi-tap approach. Another desicion point is the usage of current mode vs voltage mode drivers. So be aware of all these choices before finalizing the architecture.

One of the key trends is to use more mixed-signal control loops in equalizers. As a common theme meshing with my other posts, you will see more and more mixed-signal content in future communication SoCs. For instance instead of using an analog feedback for offset compensation, one can use a finite state machine working on digital samples of the output. Such loops are much more powerful (in terms of controllability, observability and predictability). In addition, they save power - a key requirement nowdays. Of course, the two main downsides of dither and simulation methodology have to be accounted for. Much more can be written on this subject but you'll have to wait for future posts where I'll talk about merits of digital control loops and their design methodology.

Going forward, some other things I forsee

a) More adaptive Transmit equalizers rather than just programmable. We are starting to see it but it is not clear (at least to me) what is the optimum split between receiver and transmitter. ISSCC 2011 had interesting papers on this.

b) Of course, higher speeds and lossier channels with some sort of optimal power management.

c) Better modeling of Tx analog imperfections in link level modeling and its impact on BER. More understanding of non-linear effects and inclusion in link modeling.

d) On the circuit side meeting the required accuracy and swing levels will continue to challenge and require close cordination between spec writing and system simulations.

 Comments are welcome especially to see the future trends.