PLLs - part deux

Good things come in doubles. And PLLs (phase locked loop) are no exception. In this write-up I am going to write about future PLL architectures as well as utlilize our knowledge of PLLs to understand CDRs (clock data recovery). This will also serve as a primer for future discussions on analyzing non-linear systems.

As processes become more digital centric, a future move towards digital PLLs make sense. Such PLLs are much more tolerant to PVT (process, voltage, temperature), have lower area (no caps) and much better observability, debuggability, programmability to name a few. The downside could be possible higher jitter (due to additional quantization noise sources).

However, the biggest obstacle is the lack of knowledge and resistance among traditional analog PLL practioners. Digital PLLs are much more complicated to understand (especially if you are an expert in analog PLLs :-)). One has to write an event driven simulator since that is the only way to simulate a truly non-linear system. Try explaining that to an analog designer. Ultimately, the pay-off in terms of long-term gain vs short term pain is worthwhile.

A few of the key architectural discussions in digital PLL center around nature of Phase detector(PD). Do you want a TDC or bang-bang? Another key consideration is the need for a sigma delta/dithering on the DCO to lower quatization noise. And lastly how do you find your Integral and Proportional gain coefficients. This is still a nascent field judging by the number of papers in this years ISSCC (2011).

Some good material is listed here.

1) All-Digital Frequency Synthesizer in Deep-Submicron CMOS

Texas Instruments

2) Phase Lock Techniques, 3rd ed

Gardner

Before I scare you, remember teams have shown the applicability of Digital CDR for GSM applications (which are one of the toughest specifications to meet in the world). So you can bet a digital PLL or two is in your future.

As an interesting side-note, its instructive to see how PLLs have progressed over time. The initial frequency synthesizers were almost fully analog. Perhaps you had a mixer as phase detector and the output was a voltage which went into an opamp-based loop filter. Finally into a VCO. This was followed by the popular scheme of Gardner type PLLs with a PFD, Charge pump and analog VCO. At this point people started talking about z-domain modeling and viewing PLL as a sampled system. The popularity of All digital PLLs in recent years even obviates the need of Charge pumps.

Now lets briefly touch upon CDR (clock data recovery). Many folks view this is a seperate discipline but the origins of CDR happened from PLLs and there is a lot of benefit in understanding both together.

A CDR is nothing more than a PLL with a few key differences

a) There is a transition density factor which comes into play and effects the loop parameters.

b) Typical (Bandwidth/input data) ratio in CDR is much lower than PLL.

c) Latency is a much bigger factor in CDR.

d) We care a lot about non-linear large signal effects which play into Receiver performance - Jitter tolerance, Jitter transfer etc.

Like a PLL, a CDR can be analog centric or digital. In the former there is a CDR for each lane of input data with its own VCO and control voltage. The VCO is typically centered close to a reference clock (hopefully the solution has a local reference clock. If not, we have to use referenceless frequency acquisition). Then the PD (phase detector) of the CDR will take care of the final phase locking. Historically analog CDR was the architecture of choice.

Majority of the high count serdes take advantage of a digital CDR. A PLL/DLL distribute clocks to the local lanes all of which contain only a PI (phase interpolator). The digital CDR sends a code to the PI which dictates the mixing of the phases of the clocks to generate the sampling clocks. One of the changes you see wrt digital PLL is the fact that a digital CDR only has a Phase detector. This phase detector could be Mueller-muller or an early-late alexander style one.

Remember CDRs have their own idiosynchranouses (eg false locking, hang-up etc) so be careful and understand these subtle concepts.

PLL - Just another control system

A  PLL is just another control system which works in the phase domain, ie it trys to make the phase of the output approach that of the input. phase locked loop. Viewing thus you can answer many fundamental questions on the usage and properties of a PLL. For instance, what happens to step response? Why or why not is a PLL stable? Why do you need a zero in a gardner type PLL etc etc

So how does one go about designing a PLL - whether in IC form or discrete.

a) Get your system level specifications. What is your reference frequency? What about your Output frequency. Application - RF, serdes etc.

b) From there you can find your system parameters - Bandwidth, constraints (power, area etc)

c) This gives you an idea what architecture you need for the sub-blocks. For example, VCO - ring oscillator, LC and what sub-types (quadrature, varactor based etc)

d) Follow-up with designing these components, do block level simulations and finally system level simulations for specifications such as Power, Jitter. And lots of iterations.

Simple, right :-)

Some good books for the beginner to advanced

Beginner book

1) Phase locked Loops - design, simulation and applications

Advanced Book

2) Phase Lock Techniques, 3rd ed

There is a host of literature on this topic and my list is by no means comprehensive.

I have been building PLLs since 1997 in various technologies and applications.

I remember one of the first PLLs that I helped out on was for a 622Mb/s Sonet transceiver. This was a conventional Ring oscillator based PLL. The loop filter was fully differential and it fed a v2i (voltage to current converter) that fed a current starved Ring oscillator. The PFD was your typical 2 Flop one with a delayed reset.

One of the most fundamental changes in PLLs has been the growth of LCPLLs. I remember that when inductors were first used for PLL VCOs in commercial products, they were viewed as  risky. Nowdays you see them even in microprocessors on digital substrates with massive amount of switching noise.  By my estimate this took ~7years.

I have had the fortune to design inductor based PLLs in multiple generations of VDSM (very deep sub-micron) CMOS. My latest project was for a PCIe  LCPLL. The usual challenges of low jitter, power, area etc. were compounded by PCIe requirement of tight control on loop Bandwidth. Now, the trouble arises because of a few reasons

a) Varactor modeling and variation lead to large variation in Kvco

b) Charge pump are not really current source but charge sources. Due to finite rise, fall times etc. the "effective" current from a charge pump is not the same as current source/sink

c) Variation in loop filter Resistance

So some innovative solutions need to be used to meet the specifications. Some  ideas include

- methods to measure PLL Bandwidth and peaking on-die and auto-calibrate out errors

- Linearizing Kvco through ac-coupling caps

- Increasing charge pump switching speeds by moving away from cascode switching

- Using schemes which don't have a loop resistance. Examples: Self-biased or Sample-reset filters

Also do remember to use the correct Charge pump (HiZ) and VCO (LC VCO) to get your jitter low enough to meet your jitter requirements.

Drop me a note in case you want more ideas on the effectiveness of certain techniques to meet your architectural specifications.

There are quite a few articles out there on PLLs. However, finding an article on debuggability/ practical issues with PLLs is not readily available. So I am listing a few

a) Make Feedback divider faster than VCO. At startup your VCO might have a railed control voltage and may run much faster than you simulated for

b) Shield your VCO input control voltage. This is your most sensitive node. If you want to bring it for observability put a low leakage buffer on this pin

c) Avoid chicken-and-egg problems. When integrating the PLL with your ASIC your ASIC may depend upon a clean PLL clock to propogate certain states to the PLL boundary whereas the PLL may need certain states from the ASIC to lock. A way out is to use a local non-PLL clock (eg ring oscillator) just for propogating the states till the PLLs lock

d) Modeling PLL in RTL should take into account any states which cause PLL to shift frequencies or loose lock. It is not feasible to model PLL locking in a simulation involving a full-SoC. However, a basic model should involve all signals which can cause PLL to drift.

e) Model PLL in matlab etc. to ensure your PLL is always going to be stable and ideally have a damping factor > .8 in the worst case. Remember to take aging into account when doing this.

I have just scratched the surface for this very important mixed-signal component. There are host of other nuanes - for example, testing PLLs with 300fs jitter (really!), modeling/comprehending various forms of jitter etc. etc. My next topic will focus on the future of PLLs and give a flavour of how PLL techniques can be used to analyze other components (such as clock data recovery)

Remember debugging a PLL is very difficult since its a feedback loop. Be thorough and diligent in all your circuit and system level checks. Good luck!