Mar 4, 2011

PLLs - part deux

Good things come in doubles. And PLLs (phase locked loop) are no exception. In this write-up I am going to write about future PLL architectures as well as utlilize our knowledge of PLLs to understand CDRs (clock data recovery). This will also serve as a primer for future discussions on analyzing non-linear systems.

As processes become more digital centric, a future move towards digital PLLs make sense. Such PLLs are much more tolerant to PVT (process, voltage, temperature), have lower area (no caps) and much better observability, debuggability, programmability to name a few. The downside could be possible higher jitter (due to additional quantization noise sources).

However, the biggest obstacle is the lack of knowledge and resistance among traditional analog PLL practioners. Digital PLLs are much more complicated to understand (especially if you are an expert in analog PLLs :-)). One has to write an event driven simulator since that is the only way to simulate a truly non-linear system. Try explaining that to an analog designer. Ultimately, the pay-off in terms of long-term gain vs short term pain is worthwhile.

A few of the key architectural discussions in digital PLL center around nature of Phase detector(PD). Do you want a TDC or bang-bang? Another key consideration is the need for a sigma delta/dithering on the DCO to lower quatization noise. And lastly how do you find your Integral and Proportional gain coefficients. This is still a nascent field judging by the number of papers in this years ISSCC (2011).

Some good material is listed here.
1) All-Digital Frequency Synthesizer in Deep-Submicron CMOS
2) Phase Lock Techniques, 3rd ed

Before I scare you, remember teams have shown the applicability of Digital CDR for GSM applications (which are one of the toughest specifications to meet in the world). So you can bet a digital PLL or two is in your future.

As an interesting side-note, its instructive to see how PLLs have progressed over time. The initial frequency synthesizers were almost fully analog. Perhaps you had a mixer as phase detector and the output was a voltage which went into an opamp-based loop filter. Finally into a VCO. This was followed by the popular scheme of Gardner type PLLs with a PFD, Charge pump and analog VCO. At this point people started talking about z-domain modeling and viewing PLL as a sampled system. The popularity of All digital PLLs in recent years even obviates the need of Charge pumps.

Now lets briefly touch upon CDR (clock data recovery). Many folks view this is a seperate discipline but the origins of CDR happened from PLLs and there is a lot of benefit in understanding both together.
A CDR is nothing more than a PLL with a few key differences
a) There is a transition density factor which comes into play and effects the loop parameters.
b) Typical (Bandwidth/input data) ratio in CDR is much lower than PLL.
c) Latency is a much bigger factor in CDR.
d) We care a lot about non-linear large signal effects which play into Receiver performance - Jitter tolerance, Jitter transfer etc.

Like a PLL, a CDR can be analog centric or digital. In the former there is a CDR for each lane of input data with its own VCO and control voltage. The VCO is typically centered close to a reference clock (hopefully the solution has a local reference clock. If not, we have to use referenceless frequency acquisition). Then the PD (phase detector) of the CDR will take care of the final phase locking. Historically analog CDR was the architecture of choice.

Majority of the high count serdes take advantage of a digital CDR. A PLL/DLL distribute clocks to the local lanes all of which contain only a PI (phase interpolator). The digital CDR sends a code to the PI which dictates the mixing of the phases of the clocks to generate the sampling clocks. One of the changes you see wrt digital PLL is the fact that a digital CDR only has a Phase detector. This phase detector could be Mueller-muller or an early-late alexander style one.

Remember CDRs have their own idiosynchranouses (eg false locking, hang-up etc) so be careful and understand these subtle concepts.

1 comment:

  1. Hi Rohit - nice blog! You're right about going digital, we've done this for plls and regulators for 40nm at Broadcom - now the most area consuming part of the IP blocks are the pads ;) I think the next thing will be algorithm-based with a small processor, kind of like what HS Lee has started at MIT.