Dec 10, 2012

Silicon IP and standards - Double trouble

Recently I got an opportunity to work on the newest generation of Silicon technology while implementing a new interface standard. Note, there are two "new" in the previous sentence - making it extremely challenging. Apart from the technology challenge, there were huge business learnings from this successful project, some of which are shared below.

  • Building an Ecosystem for a new interface standard is hard...but fruitful. First to market with new standards allows the company to capture the all-important sockets and also the "halo"effect.
  • Standards are incomplete.... For instance, your interface channel will have many peaks and valleys which cannot be spec'd out. Will the silicon work in diverse systems? A systems level view is essential.
  • ...but business  needs need to be met. For instance just meeting the standards will leave no margin for an OEM in Taiwan using cheap material on his boards. And the answer is not over-design :-)
  • ...and yield has to be there. How many IP providers have comprehensive programs to put in debug hooks and understand DPM goals of their customers. Designing with newest process technology requires a different mindset for making the yield numbers work.

With the advent towards semiconductor companies aquiring the interface IP, it becomes critical for  IP providers to comprehend the learnings mentioned above. There is still a chasm between what IP providers deliver and what their customers want leading to customization requests. What is needed is a predictable, high quality delivery business model understanding customers business (rather than implementing an IEEE spec to the letter). An EDA company is a good industry to take on this challenge.

Thanks for reading !


  1. Hi Rohit
    Excellent article. Very few people have written about the need for yield in IP.

  2. Good article. Can you explain how to get margin without over-design. How can you get margin without guardbanding

  3. over-design means you take the absolute worst case of everything in the system. eg worst silicon, worst board, worst PVT conditions. I don't know that many interface IP providers who would do a stastical analysis at the system level. Heck, even some silicon vendors don't do system level stastical analysis.