Feb 27, 2011

Productization - at last some discussion.

One of the requirements for a successful serdes project is the ability to sell it in high volume. Unfortunately many designers (especially IP designers) may not be aware of the methodology required for productizing a serdes. I am speaking from experience since I learnt this the hard way.

Once a design comes back from fabrication, multiple steps happen (some in parallel, others slightly staggered)
a) Wafer sort
b) System validation
c) Bench debug
d) Part characterization
e) High volume testing
f) Misc (burn-in, JTAG, margining)

Wafer sort is the process of testing at the wafer level and marking the bad dies so that they are not assembled (and packaging costs can be saved). Quite a few folks  believe this is not a valuable exercise though my experience has been otherwise. BIST (eg local loopback from the Tx to the Rx) is something testable at this point which we used. Some dc structural tests can also be tested during wafer sort. This is also the point of pre-trimming your critical analog blocks. I had designed a flow for trimming the bandgaps and voltage regulators to occur at wafer sort. These are quite complicated flows due to the chicken-and-egg problems (eg. PLLs may need bandgaps to lock but bandgap may need PLL clocks for propogating control signals to it)

Bench debug is the process whereby the part is tested in the lab with close interaction with the designer. This typical proceeds in parallel with high volume testing. Bugs from both of these flows are disposed of by the design engineering teams. At is at this point that all the choices you made defining DFx (design for debug, design for manufacturing etc) become apparent in terms of their value. This is one of the prime reasons to having digital control loops for your analog data path. For instance, you want to see control loop settling with a step change on your input. You want to view the control register bits on Logic analyzer. These are some questions you need to think about and talk with your validation team. Remember to ensure these post-silicon validation folks really stress the part to wring out all the bugs from the part. 

Characterization is high volume electrical validation of the part. It consists of 2 sub-steps.
a) Run the part on tester with a more elaborate test program. This helps to setup your guardbands and is also the fastest way to get high volume data. An example of design related feedback would be to ensure that your signal of interest is visible on the pins that interface with the tester and have no dependency upon the functioning of other parts of your SoC. As an example, ensure that PLL lock is visible on the test out pin of the part and doesn't depend upon the PLL actually locking! Sounds trivial but you'd be surprised as to the effort involved in this.
b) Run the part on the various platforms. This is needed for characterizing non-HVM tested parameters. If you're not clever this could turn out be a huge time sink and you may not get timely data for your next part revision. For instance, the rise and fall time of the part can be tested part-by-part. A better way is to put a RF switch to select 1 out of say 40 lanes with the output going to the measuring instrument. By cycling through the 40 lanes, a stastically significant sample size can be tested time effectively.
In addition, a requirement unique to serdes is the different platforms its required to work with. For instance it should be able to work with short channels, long channels, different crosstalk profile connectors etc. Remember just testing with long channels doesn't gaurantee good results with a short channel. Also interoperability with different parts quickly makes this is an intractable problem which requires thinking and innovative approaches.

High volume testing is the ultimate validation that will be run on every part before shipping to customers. Some serdes standards specify requirements which make HVM easier. Loopback is a prime example of this. However, one can go one step further. For instance, we could stress an eye using the Transmit loop filter and then loop back a stressed eye. These and other such ideas can be brought back during the design phase to make a more complete test strategy. 
Some questions to ask when you plan your HVM strategy
How much yield should you shoot for.
What is the DPM target for the product.
These factors flow into your design targets. eg offsets, monte-carlo requirements

As the reader can see, productization is not a simple task. It takes multiple product cycles before the design and validation teams become good in this. Such skills are rare and documentation is even rarer since its not discussed in conferences/journals. Happy debugging!

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